As ICs continue to decrease in size in pursuit of higher device density and production efficiency, the aspect ratios of topographical features, e.g., STI, in small regions, e.g., static random access memory (SRAM) cells, are restricted, e.g., widening the STI has a large impact on the layout area and depth of the STI is limited by the aspect ratio and process complexity. A combination of both a shallow and deep isolation is required to enable increased flexibility in the well bias but poses the challenge that the deep isolation must fully electrically isolate two adjacent well regions.
A need, therefore, exists for devices with extended STI depth with a reduced critical dimension (CD) with reduced leakage, and for enabling methodology.